Phase locked loop systems are well known in the prior art. These loops are typically used to maintain stable frequency, phase and other circuit parameter. Phase locked loops must have stable and controlled operating characteristics, immune to voltage, temperature and circuit fabrication variations. This is especially so during the operation of the phase locked loop when environmental conditions can change readily. Primary parameter which are essential for the operation of a stable phase locked loop are loop gain and filter characteristics.
One type of prior art integrated phase locked loop typically allows off-chip adjustment to control the loop parameters. This is achieved by adjusting the loop filter, or changing the loop gain and are typically made with respect to an external standard reference.
Another type of prior art integrated phase locked loop typically uses a secondary loop to control the loop parameter which are also immune to temperature, process, and other operating environment variations. This type of prior art dual loop phase locked loop is described in U.S. Pat. No. 4,829,258, issued on May 9, 1989, and entitled STABILIZED PHASE LOCKED LOOP. FIG. 1 illustrates in block diagram form the structure of the prior art dual loop phase locked loop.
As can be seen from FIG. 1, reference loop 11 of the prior art dual loop phase locked loop 10 provides analog trim signals V.sub.FB1 and I.sub.OS1 to charge pump 21, loop filter 22, transconductance amplifier 23, and fixed gain current source 24 of primary loop 12 of phase looked loop 10. The analog trim signals V.sub.FB1 and I.sub.OS1 are used to compensate for various parameter variations in primary loop 12. This allows the prior art dual loop phase locked loop to be immune to process and operating environment variations. Furthermore, the loop can be programmed to different data rates by adjusting the reference clock signal.
Disadvantage are, however, associated with the prior art dual loop phase locked loop. One disadvantage is that the loop filter of the prior art dual loop phase locked loop includes two capacitors 22a and 22c, the capacitances of which are not independent of each other. This typically causes the loop filter characteristics to be difficult to accurately set and adjust, therefore affecting the performance of the loop filter. The capacitance dependency of the two capacitors 22a and 22c is typically due to the parasitic capacitance in each of the two capacitors. Because of the unpredictable nature of the parasitic capacitance, the capacitance of each of the two capacitors in the loop filter typically cannot be accurately set and adjusted.
Another disadvantage of this prior art dual loop phase locked loop is that the loop filter circuit of the prior art phase locked loop typically requires the power supply voltage V.sub.CC to be higher than 3 volts. As can be seen from FIG. 1, loop filter 23 typically has capacitor 22a serially connected to transistor 22b. Capacitor 22c is connected in parallel with transistor 22b. Given that two or more components are typically connected together serially, this prior art loop filter cannot typically function satisfactorily and properly when the power supply voltage V.sub.CC is below 3 volts. This means that the prior art loop filter circuit typically is not used in a 3 volt power supply environment. This drawback is not trivial given that many laptop computers employ a 3 volt power supply.